1. Field of the Invention
Embodiments of the present invention relate generally to integrated circuit chip packaging and, more specifically, to a microelectronic package with a stress-tolerant solder bump pattern.
2. Description of the Related Art
In the packaging of integrated circuit (IC) chips, the so-called “2.5D” packaging approach has been used for various multi-chip packages, such as field-programmable gate arrays (FPGAs), central processing units (CPUs), or graphics processing units (GPUs) packaged together with one or more dedicated memory chips. In the 2.5D packaging approach, two or more IC chips are mounted on a silicon interposer substrate and electrical connections between the IC chips are formed on the silicon interposer. In addition, the interposer substrate is configured with through-silicon vias (TSVs), which are vertical electrical pathways that pass through the interposer substrate and facilitate electrical connection of IC chips mounted on one side of the interposer to a packaging substrate mounted on the other side of the interposer. Compared to wire-bonded IC chips, TSVs offer reduced parasitic capacitance, better performance, reduced power loss, and a require less area.
Because 2.5D packaging enables multiple IC chips to be incorporated into a single package, and because the IC chips are typically distributed over a silicon interposer without vertical stacking, the silicon interposer is essentially a very large chip. Consequently, significant mechanical stresses can occur in a 2.5D chip package during operation due to the significant mismatch in coefficient of thermal expansion of the silicon interposer and the organic packaging substrate. This mechanical stress can affect reliability of such IC packages by causing failure of solder bumps connecting the interposer to the packaging substrate, including solder bump cracking and delamination of solder bumps from interface layers.
Accordingly, there is a need in the art for an IC package that can better withstand the increased mechanical stresses that can occur when large surface area interposers are used.